CLOCK BUFFER FAMILY

KGFH, KGFV, KGFU


Cell Description
Cell Name BC AREA[au] Function
KGFH 12 480 Global Clock Buffer with Enable (High Power Type)
KGFV 22 880 Global Clock Buffer with Enable (Very High Power Type)
KGFU 37 1480 Global Clock Buffer with Enable (Ultra High Power Type)

Cell Symbol
Symbol

Function Table

Inputs

Memory

Output

CK

G

M

X

H

L

=

(M)

H

H

=

(M)

L

L

L

L

L

H

H

L


Pin Parameter
[KGFH]
Name Load[fF] Drive[fF] Max Tsin[ps] Pi[nW/MHz/V^2] I/O
CK 21 - 500 109.700 Input
G 7 - 1500 15.417 Input
X - 4751 - - Output
[KGFV]
Name Load[fF] Drive[fF] Max Tsin[ps] Pi[nW/MHz/V^2] I/O
CK 22 - 500 199.211 Input
G 7 - 1500 15.444 Input
X - 8996 - - Output
[KGFU]
Name Load[fF] Drive[fF] Max Tsin[ps] Pi[nW/MHz/V^2] I/O
CK 22 - 500 381.233 Input
G 7 - 1500 15.406 Input
X - 18428 - - Output

Propagation Delay Parameter
Input Slew Rate: Tsin => MIN TYP MAX
[KGFH]
Path Tsin[ps] T0[ps] Tout[ps]
Load[fF] 0 24 72 216 648 1728
CK(D)->X(D) 210 193 0 13 35 87 214 510
CK(U)->X(U) 210 252 0 12 31 75 175 389
[KGFV]
Path Tsin[ps] T0[ps] Tout[ps]
Load[fF] 0 48 144 432 1296 3456
CK(D)->X(D) 210 258 0 12 32 82 209 517
CK(U)->X(U) 210 298 0 9 24 58 144 352
[KGFU]
Path Tsin[ps] T0[ps] Tout[ps]
Load[fF] 0 96 288 864 2592 6912
CK(D)->X(D) 210 302 0 12 33 84 211 514
CK(U)->X(U) 210 347 0 10 24 60 147 355

Output Slew Rate Parameter
Input Slew Rate: Tsin => MIN TYP MAX

Timing Parameter
[KGFH]
Pin Type Symbol Max[ps]
CK WIDTH TCKW 162
G, CK SETUP TSG 432
CK, G HOLD THG 75
[KGFV]
Pin Type Symbol Max[ps]
CK WIDTH TCKW 132
G, CK SETUP TSG 412
CK, G HOLD THG 67
[KGFU]
Pin Type Symbol Max[ps]
CK WIDTH TCKW 133
G, CK SETUP TSG 410
CK, G HOLD THG 70

Definition of Parameters
Chart

Equivalent Circuit
[KGFH]
Equiv